Linux 6.19 Release – Main changes, Arm, RISC-V, and MIPS architectures

https://fed.brid.gy/r/https://www.cnx-software.com/2026/02/09/linux-6-19-release-main-changes-arm-risc-v-and-mips-architectures/

#KrsteAsanović, co-founder of #SiFive and a key figure in the development of #RISCV, discusses the #opensource #CPU architecture’s origins and evolution. Initially created for academic research at Berkeley, RISC-V’s modular design allowed for rapid prototyping and software development. The architecture’s openness attracted interest from both academia and industry. https://morethanmoore.substack.com/p/an-interview-with-dr-krste-asanovic?eicker.news #tech #media #news

Ah, another brave soul attempts to shoehorn #xv6 into the almighty #SiFive HiFive Unmatched board. 🤡 Because #porting an archaic educational OS to a niche board is exactly what the world needed right now. 🙄 #GitHub, of course, stands by to witness this monumental achievement in software archaeology. 🥳
https://github.com/eyengin/xv6-riscv-unmatched #HiFiveUnmatched #softwarearchaeology #educationalOS #HackerNews #ngated

Linux 6.18 release – Main changes, Arm, RISC-V, and MIPS architectures

https://web.brid.gy/r/https://www.cnx-software.com/2025/12/01/linux-6-18-release-main-changes-arm-risc-v-and-mips-architectures/

We've updated our tor relay build script for #RISCV, building #openssl and #tor from source:

https://code.disobey.net/EmeraldOnion/tor-openssl-riscv/

Notably, to get rid of this tor initialization warning:
> We were built to run on a 64-bit CPU, with OpenSSL 1.0.1 or later, but with a version of OpenSSL that apparently lacks accelerated support for the NIST P-224 and P-256 groups. Building openssl with such support (using the enable-ec_nistp_64_gcc_128 option when configuring it) would make ECDH much faster.

With an added openssl configure target and option:
> linux64-riscv64 enable-ec_nistp_64_gcc_128

Our #SiFive #HiFive RISC-V 256-bits ECDH performance is synthetically boosted:

From:
> 256 bits ecdh (nistp256) 0.0029s 340.7

To:
> 256 bits ecdh (nistp256) 0.0005s 2057.1

This is a 6x P-256 handshakes boost, so this should help speed up this Tor exit relay. We are only running one Tor daemon on this hardware to see how well it does.

Upbeat and SiFive Launch Ultra-Low Power RISC-V MCU with AI Acceleration

https://fed.brid.gy/r/https://linuxgizmos.com/upbeat-and-sifive-launch-ultra-low-power-risc-v-mcu-with-ai-acceleration/

Kickstarterová kampaň na odlehčenou verzi VisionFive 2 spuštěna
#SiFive #RISC-V
https://alt-f4.cz/kickstarterova-kampan-na-odlehcenou-verzi-visionfive-2-spustena

StarFive VisionFive 2 Lite is a cheap(er) RISC-V single-board computer (crowdfunding)

The VisionFive 2 Lite is a credit card-sized single-board computer (SBC) that looks a lot like a Raspberry Pi. But it’s actually a smaller, cheaper, and less powerful version of the VisionFive 2 RISC-V SBC that launched a few years ago.

The new model has a slower version of the same processor and loses a few ports and connectors, but picks up optional support for onboard WiFi and Bluetooth. […]

#crowdfunding #riscV #sbc #sifive #starfive #starfiveVisionfive2Lite

Read more: https://liliputing.com/starfive-visionfive-2-lite-is-a-cheaper-risc-v-single-board-computer-crowdfunding/

SiFive X280 RVV benchmarks: https://camel-cdr.github.io/rvv-bench-results/tt_x280/index.html

Civil was so nice to run my rvv benchmark on the SiFive X280 cores on the Tenstorrent Blackhole.

#riscv #rvv #Tenstorrent #sifive

SiFive and Red Hat Collaborate to Bring RHEL 10 to RISC-V Development

https://fed.brid.gy/r/https://linuxgizmos.com/sifive-and-red-hat-collaborate-to-bring-rhel-10-to-risc-v-development/

Red Hat Enterprise Linux (#RHEL) 10 aka #RHEL10 is now officially out:

https://www.redhat.com/en/about/press-releases/red-hat-introduces-rhel-10

https://www.redhat.com/en/blog/whats-new-rhel-10

Release notes: https://docs.redhat.com/en/documentation/red_hat_enterprise_linux/10/html/10.0_release_notes/index

More docs: https://docs.redhat.com/en/documentation/red_hat_enterprise_linux/10/

Related news:

* Post-quantum cryptography in RHEL10 https://www.redhat.com/en/blog/post-quantum-cryptography-red-hat-enterprise-linux-10

* #RedHat partners with #SiFive for a #RISCV developer preview of RHEL10: https://www.redhat.com/en/blog/red-hat-partners-with-sifive-for-risc-v-developer-preview-for-red-hat-enterprise-linux-10

A #RISCV Progress Check: Benchmarking #P550 and #C910
The RISC-V cores fall short of Ar #CortexA73 and well short of Intel’s #Goldmont Plus. Mediatek’s In-Order #Genio1200 hyas higher clock speeds and better DRAM latency than C910 and P550. Its #CortexA55 cores are able to catch C910 and P550 without out-of-order execution.
#SiFive’s P550 and T-HEAD’s Xuantie C910 are both notable for featuring out-of-order execution on RISC-V. Both are plagued by low clock speeds.
https://chipsandcheese.com/p/a-risc-v-progress-check-benchmarking

Inside #SiFive’s #P550 #RISCV Microarchitecture
It doesn’t go head-on against likes of AMD’s Zen 5, Intel’s Lion Cove, or Qualcomm’s Oryon. P550’s out-of-order engine is closer in size to something like Intel’s Core 2 from over 15 yrs ago. Combine that with much lower clock speeds than even what Core 2 ran at, and P550 is really a low power core with modest performance. This core aims for “30% higher performance in less than half the area of a comparable Arm Cortex A75.”
https://chipsandcheese.com/p/inside-sifives-p550-microarchitecture

@zilahu és akkor még egy friss-ropogós teszt a Si-Five USA cég HiFive Premier P550 alaplapjáról https://www.youtube.com/watch?v=1565YYsFmd4 #risc-v #sifive #p550 #test

RISC-V Mainboard for Framework Laptop 13 is now available
🔗 https://frame.work/si/en/blog/risc-v-mainboard-for-framework-laptop-13-is-now-available
via @frameworkcomputer

"We’re happy to share that DeepComputing’s DC-ROMA RISC-V Mainboard for Framework Laptop 13 is now in stock and shipping in the Framework Marketplace. This is very much a developer-focused board to help accelerate maturing the software ecosystem around RISC-V."

#RISCV #RISC_V #laptop #laptops #hardware #CPU #CPUs #Framework #DeepComputing #StarFive #JH7110 #SiFive #U74

Inside #SiFive P550 (#RISCV ESWIN EIC7700X)

https://chipsandcheese.com/p/inside-sifives-p550-microarchitecture

Inside SiFive’s P550 Microarchitecture
🔗 https://old.chipsandcheese.com/2025/01/26/inside-sifives-p550-microarchitecture/

"The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

#RISCV #RISC_V #ComputerArchitecture #CPU #CPUs #Processor #Processors #Hardware #ComputerHardware #Eswin #EC7700X #SiFive #P550

"#SiFive opens China office" (#RISCV)

https://finance.yahoo.com/news/tech-war-us-firm-sifive-093000815.html

32GB P550 board bring up!

https://www.youtube.com/watch?v=9KTbi8dJjzQ

#risc_v #p550 #sifive

#SiFive #HiFive Premier #P550 #RISCV Price Lowered to $399, ready to go with #Ubuntu 24.04 LTS Support
This RISC-V developer board features the SiFive P550 CPU, 128GB eMMC storage, 16GB or 32GB of LPDDR5 memory, PCIe connectivity, M.2 storage support, USB 3, and more.
https://www.phoronix.com/news/HiFive-Premier-P550-Drop